Avenue de la Boulaie-CS 47601
35576, Cesson-Sévigné, France
Tel: +33 299 84 45 41
This website is Work In Progress
I am an Associate Professor of Electrical and Computer Engineering at CentraleSupélec, with a reasearch appointment at the IETR (Institut d’Électronique et des Technologies du numéRique) in Rennes, France.
My research interests span the areas of embedded computing architectures, reconfigurable computing, hardware security and self-adaptive systems. I work on building reconfigurable architectures for adaptive hardware, designing and programming novel accelerator architectures and digging around with hardware security. Recently, I started working on hardware security for machine learning, specifically on side-channel attacks resistant implementations of DL hardware accelerators. Overall, my research work aims at building more efficient, secure and intelligent systems.
Previously, I was an Assistant Professor (2017–2019) and Teaching Assistant (2012–2017) at UPM (Technical University of Madrid).
I obtained my PhD (2015) in Electrical & Computer Engineering at CEI (Center of Industrial Electronics, UPM) working on evolvable hardware in FPGAs, under the supervision of Professors Eduardo de la Torre (CEI, UPM) and Lukáš Sekanina (Brno University of Technology).
Even before that I was a Research Assistant (2006–2011) at CEI, UPM, and a Research Engineer (2005–2006) at INSIA (Intelligent Vehicle Systems unit, University Institute for Automobile research, UPM).
|Feb 13, 2022||This website is Work In Progress|
|Nov 7, 2015||A long announcement with details|
Appl. Sci.Physical Side-Channel Attacks on Embedded Neural Networks: A SurveyApplied Sciences