I am an Associate Professor of Electrical & Computer Engineering at CentraleSupélec in Rennes, France. I hold a joint research appointment at IETR (Institut d’Électronique et des Technologies du numéRique), SCEE team (Signals, Communications and Embedded Electronics).
My research interests lay in reconfigurable & parallel heterogeneous architectures for high performance, secure and self-adaptive embedded computing systems.
I like building adaptive hardware to enable system self-adaptation, designing and programming novel accelerator architectures (embedded AI/ML, communications) and digging around with hardware security.
Something that is increasingly driving my interest is finding ways to beautifully and efficiently combine all of the above to help building more efficient, secure and intelligent systems. And this is certainly not as straightforward as it might initially appear.
I obtained my PhD (2015) in Electrical & Computer Engineering at CEI, UPM (Center of Industrial Electronics, Universidad Politécnica de Madrid) working on evolvable hardware in FPGAs, under the supervision of Professors Eduardo de la Torre (CEI, UPM) and Lukáš Sekanina (Brno University of Technology, BUT).
Previously, I was an Assistant Professor (2017–2019) and a Teaching Assistant (2012–2017) at the School of Telecommunications Systems and Engineering, UPM; and a Research Assistant (2006–2011) at CEI, UPM and (2005–2006) at the Intelligent Vehicle Systems division, University Institute for Automobile research (INSIA), UPM.
In 2017 I was a visiting research professor for 5 months at IETR-INSA Rennes, in Rennes, France; and in 2009 a visiting research student for 4 months at the Evolvable Hardware Research group, Faculty of Information Technology, BUT, in Brno, Czech Republic.